The present invention relates to semiconductor device fabrication and more particularly to a process of fabricating an integrated circuit (IC) in which the gate conductor definition and contact etch processing are performed in the array (i.e., dynamic random access memory (DRAM) device) areas of the IC separately from those that are performed in the support (i.e., logic device) areas of the IC, such that the gate conductor linewidth is well controlled in both the array and support device areas with or without a borderless diffusion contact in the array.
In the field of semiconductor device manufacturing, merged logic DRAM devices are becoming increasingly important. This is so since the coupling of logic devices with DRAM cells provides a device which has all the benefits of DRAMs, but having the speed of conventional logic devices to improve bandwidth and performance.
In merged devices, the gate conductor linewidth control is critical to metal oxide semiconductor field effect transistor (MOSFET) parameter control. On a typical DRAM or embedded DRAM chip, there are highly nested gate conductor lines at the minimum linewidth and minimum space in the array while there are gate conductor lines which are isolated or semi-isolated from the other gate conductor lines outside the array. The gate conductor linewidth control is critical to the field effect transistors (FETs) made inside and outside of the array. In addition to minimize area taken by the array, the bitline contact must be self-aligned to the gate conductor lines. This requires a relatively thick dielectric cap on the gate conductor.
Traditionally, all gate conductor shapes on a DRAM chip are defined with one critical lithography step, a single mask etch and a single gate etch in both nested and non-nested areas of the chip. The prior art processes are optimized for the array linewidth control to simultaneously achieve a borderless contact, and tight array gate conductor linewidth tolerance, yet not bridge the closely spaced gate conductor resist. Despite these optimizations, prior art processes are not optimal for the support transistor linewidth tolerances.
For example, the thick nitride cap required over the gate conductor in the array areas reduces linewidth tolerances in the support areas. The resist, ARC (anti-reflective coating), exposure conditions and mask open etch are optimized for the array equal line/space at minimum dimensions. No consideration is however given in the prior art of optimizing the support gate conductor linewidth tolerance. The dielectric cap thickness, the gate conductor lithography and the gate conductor mask open etch are the main contributors to the gate conductor linewidth control.
Moreover, the present processing of DRAM structures in the array areas suffers from poor VT (threshold voltage) tolerance of small geometry array devices. Standard scaling rules which call for increased well doping concentration also cause increase electric fields that are detrimental to the several leakage constraints on the DRAM array structures. In addition, the tight spacing between the wordlines impedes standard halo implants and there are limits even with the bitline only halo implantation schemes. Consequently, there is a strong need for self-aligned halo schemes in the dense DRAM array.
In view of the drawbacks mentioned hereinabove in regard to prior art merged logic DRAM processing, there is a continued need to develop a new and improved processing scheme which provides a tight effective gate length, Leff, tolerance in the support devices as well as an improved VT tolerance in the array devices.
Good control of the gate conductor linewidth is needed to: (i) control the sub-threshold leakage current of the DRAM access transistor in the array areas because a gate conductor that is too narrow may lead to high leakage current (when the transistor is off) and therefore shorten retention time for refreshing the memory cell; (ii) control on-current of the DRAM access transistor in the array regions since a gate conductor that is too wide may lead to insufficient device current and reduced signal margin; and (iii) obtain gate conductor patterns in the support areas that are the correct width because a gate conductor that is too wide causes the transistor to switch more slowly between logic levels, and a gate conductor that is too narrow leads to undesirably high leakage current when the transistor is off.
One object of the present invention is to provide a method of fabricating a semiconductor IC in which the gate conductor linewidth is well controlled in both the array areas and the support areas of the semiconductor IC while providing a borderless contact in the array areas.
Another object of the present invention is to provide a method of fabricating a semiconductor IC in which the array VT tolerance is improved.
These and other objects and advantages are achieved in the present invention by utilizing two different gate conductor dielectric caps. The different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region.
The thinner dielectric cap is made into dielectric spacers in the array device regions during the support mask etch. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth and the resist line spacing to be wider than the final array line spacing This widens the array gate conductor processing window. Thus the second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in both the array and support device regions. The gate conductors in the array and support device regions are etched simultaneously to reduce production cost.
In a first embodiment of the present invention, the method comprises the steps of:
(a) forming a gate conductor stack on a surface of a gate dielectric, said gate dielectric is formed on a surface of a semiconductor substrate having at least one array device region and at least one support device region;
(a) forming a first gate dielectric cap on at least the gate conductor stack in said at least one array device region;
(c) selectively patterning and etching the first gate dielectric cap in said at least one array device region, said first gate dielectric cap not being present in said at least one support device region after said etching;
(d) forming a second gate dielectric cap on all exposed surfaces in said at least one array device region and in said at least one support device region, said second gate dielectric cap being thinner than said first gate dielectric cap;
(e) selectively etching said second gate dielectric cap in said at least one array device region and in said at least one support device region, wherein said second etched gate dielectric cap in said at least one support device region serves as a gate conductor mask; and
(f) simultaneously etching exposed surfaces of said gate conductor stack in both said at least one array device region and said at least one support device region stopping on said gate dielectric, wherein said simultaneous etching provides a plurality of patterned gate stacks in both said at least one array device region and said at least one support device region.
The structure provided by steps (a)-(f) may then be subjected to conventional ion implantation which forms diffusion regions in the substrate and other conventional post gate stack processing may also be employed in forming the borderless bitline contacts.
In a second embodiment of the present invention, the method comprises the steps of:
(a) forming a gate conductor stack on a surface of a gate dielectric, said gate dielectric is formed on a surface of a semiconductor substrate having at least one array device region and at least one support device region;
(b) forming a first gate dielectric cap on at least the gate conductor stack in said at least one array device region;
(c) selectively patterning and etching the first gate dielectric cap in said at least one array device region, said first gate dielectric cap not being present in said at least one support device region after said etching;
(d) forming a second gate dielectric cap on all exposed surfaces in said at least one array device region and in said at least one support device region, said second gate dielectric cap being thinner than said first gate dielectric cap;
(e) selectively etching said second gate dielectric cap in said at least one array device region and in said at least one support device region, wherein said second etched gate dielectric cap in said at least one support device region serves as a gate conductor mask;
(f) block masking said support device region;
(g) etching exposed surfaces of said gate conductor stack in said at least one array device region stopping on said gate dielectric;
(h) depositing a barrier layer over at least said array device region;
(i) depositing a dielectric layer over said array device region and said support device region;
(j) depositing and patterning a photoresist to form patterning over said support device region while protecting said array device region; and
(k) etching said gate conductor stack in said support device region.
In a third embodiment of the present invention, the method comprises the steps of:
(a) forming a gate conductor stack having an upper portion and a lower portion comprising undoped silicon on a surface of a gate dielectric, said gate dielectric is formed on a surface of a semiconductor substrate having at least one array device region and at least one support device region;
(b) forming a first gate dielectric cap on at least the gate conductor stack in said at least one array device region;
(c) selectively patterning and etching the first gate dielectric cap and said upper portion in said at least one array device region, said first gate dielectric cap and said upper portion not being present in said at least one support device region after said etching;
(d) forming a second gate dielectric cap on all exposed surfaces in said at least one array device region and in said at least one support device region, said second gate dielectric cap being thinner than said first gate dielectric cap;
(e) selectively etching said second gate dielectric cap in said at least one array device region to form sidewall spacers on said first etched gate dielectric cap;
(f) implanting a first dopant of a first charge carrier type into said exposed lower portion in said array device region;
(g) annealing said semiconductor substrate to drive said first dopant into said lower portion under said first dielectric cap;
(h) etching said exposed lower portion in said array device region;
(i) depositing a doped glass on said semiconductor substrate and removing said doped glass from said support device region;
(j) patterning said second dielectric cap in said support device region to expose and etch said lower portion in said support device region to form gate conductors;
(k) removing said second dielectric cap-on said gate conductors in said support device region and removing said gate dielectric between said gate conductors;
(l) implanting a second dopant of a second charge carrier type into said exposed lower portion of said gate conductor in said support device region; and
(m) annealing said semiconductor substrate to drive said second dopant into said gate conductors in said support device regions, whereby gate conductors of said first charge carrier type are formed in said array device region and gate conductors of at least said second charge carrier type are formed in said support device region.
Optionally, another implantation step could be employed between steps (l) and (m) to implant a third dopant of a different charge carrier type into the lower portion of the gate conductor in the support device region. A block mask could be used to direct the dopant into the specific region. When a third implantation step is employed, annealing step (m) drives in both the second and third dopant.
In a fourth embodiment of the present invention, the method comprises the steps of:
(a) forming a gate conductor stack having an upper portion and a lower portion comprising undoped silicon on a surface of a gate dielectric, said gate dielectric is formed on a surface of a semiconductor substrate having at least one array device region and at least one support device region;
(b) forming a first gate dielectric cap on at least the gate conductor stack in said at least one array device region;
(c) selectively patterning and etching the first gate dielectric cap and said upper portion in said at least one array device region, said first gate dielectric cap and said upper portion not being present in said at least one support device region after said etching;
(d) forming a second gate dielectric cap on all exposed surfaces in said at least one array device region and in said at least one support device region, said second gate dielectric cap being thinner than said first gate dielectric cap;
(e) selectively etching said second gate dielectric cap in said at least one array device region to form sidewall spacers on said first etched gate dielectric cap;
(f) etching said gate conductor stack in said at least one array device region stopping on said gate dielectric;
(g) depositing and patterning a barrier layer over said array device region to define a gate conductor mask and to define borderless contact etch openings; and
(h) etching said gate conductor stack and said support device region.